Hi, I’m Steven!

I’m an Assistant Teaching Professor in Electrical and Computer Engineering at Tufts University, where I teach a mix of topics including embedded programming, computer architecture, and imaging systems.

For Fall 2023, I am teaching:

For a full description of these and other courses I’ve taught, see my teaching page.


sbell _ ece.tufts.edu

Curtis 001-C (click here for directions)

If you’d like to schedule a meeting with me, you can see when I’m available on this calendar; send me an email if you’d like to schedule a meeting.

If you’re interested in working in my research lab, please read this first.


Ok, “news” is a stretch. Here are some things I’ve worked on in the last few years, in addition to teaching my courses:

ASEE paper on digital labs with $30 FPGAs

In June 2023 I presented on how we use the low-cost UPduino FPGA in ES 4. An inexpensive breadboardable FPGA maintains the benefits of doing hands-on work with 74-series logic while giving students experience with modern professional tools. We also build some pretty cool final projects! You can read the full paper here.

Tufts “Teaching with Technology” award

I received a 2023 Tufts “Teaching with Technology” award for my work creating VHDLweb, a tool which lets students write and simulate VHDL code in a web browser.

Traditional simulation tools have substantial installation overhead, making them impractical to use for a quick in-class exercise. They also have a steep learning curve, meaning that precious cognitive resources which could be focused on learning digital design are instead wasted navigating the peculiarities of the tool.

VHDLweb reduces both of these burdens to zero, allowing students to solve VHDL problems in class, on any device, with nothing to install and nothing sucking their focus from the task of writing code. You can try it out at vhdlweb.com. A previous award video from 2019 discusses the genesis of VHDLweb.

VHDLweb updates

In early 2020 I rebuilt VHDLweb from scratch to improve the user experience and capture more useful data. I’m now looking for one or two eager students to help analyze all of the data from Spring 2020, with the goal of understanding how students learn VHDL and digital design more generally. I’m also looking for help adding several new features to VHDLweb. Get in touch with me if you’re interested.